1. Field of the Invention
This invention concerns a zero string error detection circuit which detects a string of zeros in bipolar data.
In digital transmission for audio data and other data, for example, the clock for playback synchronization and data recognition is extracted from the audio data. The clock cannot be extracted if zeros occur in succession as in the condition of no sound. If data is transmitted in 8-bit units, eight successive zeros are converted to an 8-bit code (B8ZS code) in a specific pattern. If data is transmitted in 6-bit units, six successive zeros are converted to a 6-bit code (B6ZS code) in a specific pattern.
At the receiving end, this code, when detected, is returned to the original string of zeros. This means that normally, no zero signal should be detected during the period from the time of conversion at the transmitting end to the time of restoration at the receiving end.
However, when a fault occurs in the transmission path or other facilities, zero signals may occur. Therefore, transmission systems are designed so that when a specified number of zero bits are detected, a signal indicating a zero string error (zero string error detection signal) is issued and when the zero string error detection signal is issued a number of times in succession, an alarm is issued to the transmitting end.
2. Description of the Related Art
FIG. 6 is a circuit diagram of a conventional zero string error detection circuit. In this figure, 1P and 1N represent shift registers. Shift register 1P receives the positive side of serial bipolar data P and converts it to parallel data composed of a specific number (8, for example) of bits. Shift register 1P receives the negative side of serial bipolar data N and converts it to parallel data composed of a specific number (8, for example) of bits.
Component 2 is a B8ZS code detector. When it receives a B8ZS code (000VB0VB, where V is a code which indicates that the data does not conform to the coding rule and B is a code which indicates that the data conforms to the coding rule--for example, if the output of shift register 1P is 00010001 and the output of shift register 1N is 00001010, the B8ZS code is detected) from parallel outputs FF1-FF8 and FF1'-FF8' from the shift registers, it issues a reset signal FRST to shift registers 1P and 1N to make the 1P and 1N outputs zero.
Components 3P and 3N are 8-bit zero monitors. Eight-bit zero monitor 3P outputs a zero string error detection signal when it finds a string of eight bits of zero in bipolar data P. Eight-bit zero monitor 3N outputs a zero string error detection signal when it finds a string of eight bits of zero in bipolar data N. As indicated in FIG. 7, eight-bit zero monitors 3P and 3N are fitted with an eight-bit shift register 3P-1 (3N-1) and a NOR gate 3P-2 (3N-2) which receives the output of shift register 3P-1 (3N-1).
The zero string detection signals are fed via an AND gate to an alarm controller which is not shown. When the alarm controller detects the zero string detection signal a specific number of times in succession, it sends an alarm to the transmitting end or other components.
Component 5 is an OR gate for extracting output data. It receives the sixth outputs FF6 and FF6' of shift registers 1P and 1N and outputs their OR as serial data.
When B8ZS code detector 2 detects a B8ZS code in outputs from shift registers 1P and 1N in the above configuration, it issues a reset signal FRST to shift registers 1P and 1N to make the outputs of shift registers 1P and 1N zero. As a consequence, the B8ZS code is returned to eight bits of zero.
If zeros occur in succession because of a fault in the transmission path or other components, eight-bit zero monitors 3P and 3N issue zero string error detection signals, respectively. If the zero string error detection signals are issued a number of times in succession, the alarm controller issues an alarm to the transmitting end.
Zero string error detection systems where a B6ZS code is detected have similar configurations and functions.
The above conventional zero string error detection circuit with a B8ZS code converter involves a problem that a large-scale gate circuit must be used because zero strings are detected both in bipolar data P and in bipolar data N.
A similar problem is involved in a zero string error detection circuit which handles B6ZS codes.